1. Field of the Invention
The present invention relates to a semiconductor memory device including a floating gate electrode and control gate electrode, and a method of manufacturing the same.
2. Description of the Related Art
Conventionally, a nonvolatile semiconductor memory device including a floating gate electrode FG and control gate electrode CG has been proposed as a semiconductor memory.
In this nonvolatile semiconductor memory device, as shown in FIG. 23, a floating gate electrode FG, interelectrode insulating film 208, and control gate electrode CG are processed into a desired shape, and a gate sidewall oxide film 212 is formed on the entire surface by oxidation after that. When the gate sidewall oxide film 212 is formed, however, thick so-called “bird's beak” oxidation regions 213 are formed in the upper and lower end portions of the interelectrode insulating film 208. This decreases the electric capacitance of the interelectrode insulating film 208, and causes faulty operations of the memory device. These problems caused by the formation of the bird's beak oxidation regions 213 similarly arise when a high-k oxide film such as a hafnium oxide film, zirconium oxide film, or tantalum oxide film, or an insulating film obtained by adding an impurity to a high-k oxide film like this is used as the interelectrode insulating film 208.
As a method of avoiding the formation of the bird's beaks described above, a technique as shown in FIGS. 24A and 24B is disclosed (e.g., Jpn. Pat. Appln. KOKAI Publication No. 7-249697, 8-153814, or 9-219459). In this technique, silicon nitride layers 231 and 232 are formed in the upper and lower interfaces of an interelectrode insulating film 208, thereby preventing the penetration of an oxidation species during gate sidewall oxidation and preventing the formation of bird's beaks.
This technique discloses CVD (Chemical Vapor Deposition) or thermal nitriding as the method of forming the silicon nitride layers 231 and 232. However, the following problems arise if the silicon nitride layers 231 and 232 are formed by using CVD or thermal nitriding.
When CVD is used, the total physical film thickness of an interelectrode insulating film 208a between a control gate electrode CG and floating gate electrode FG increases. Therefore, as shown in FIG. 24B, the depth P of the control gate electrode CG buried between adjacent cells decreases. This decreases the capacitance of the interelectrode insulating film 208 and increases the parasitic capacitance between the adjacent cells, so the memory device suffers faulty operation. In addition, the width Q of the control gate electrode CG buried between the adjacent cells decreases. Since this depletes the buried portion of the control gate electrode CG, the memory device suffers faulty operation. Furthermore, if the depth P is well increased, the distance R between a substrate 201 and the interelectrode insulating film 208 shortens. This decreases the breakdown voltage between the substrate 201 and control gate electrode CG, so the memory device suffers faulty operation. These problems are significant when the depth P, width Q, and distance R are approximately 100 nm or less.
On the other hand, when thermal nitriding is used, a high-temperature, long-time thermal budget is necessary to form silicon nitride layers 231 and 232 having a thickness which prevents the formation of bird's beaks. Since this degrades the quality of a tunnel oxide film 202, the reliability of the memory device is also degraded.